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Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
K4S56163LC-RF(R)
CMOS SDRAM
16Mx16 Mobile DRAM
(TCSR & PASR option support)
Revision 0.4 December 2001
Rev. 0.4 Dec. 2001
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
K4S56163LC-RF(R)
Revision History
Revision 0.0 (April. 2001, Target)
* First generation of 256Mb Low Power SDRAM having TCSR option. (V DD 2.5V, VDDQ 1.8V).
CMOS SDRAM
Revision 0.1 (June 20. 2001, Target)
* Changed device name from low power sdram to mobile dram.
Revision 0.2 (August 10. 2001, Preliminary)
* Change of tSAC from 6ns to 6.5ns in case of -1L part, from 7ns to 7.5ns in case of -15 part. * Change of tOH from 3ns to 3.5ns. * Change V IH min. from 1.44V to 0.8xV DDQ and V OH min. from 1.6V to 0.9xV DDQ
Revision 0.3 (October 6. 2001, Preliminary)
* Changed DC current. * Changed of CL2 tSAC from 6ns to 7ns for -75 part. * Changed of CL3 tSAC from 6ns to 7ns and CL2 tSAC from 6ns to 8ns, CL1 tSAC from 18ns to 20ns for -1L part. * Changed of CL2 tSAC from 7ns to 9ns and CL2 tSAC from 7ns to 9ns, CL1 tSAC from 22ns to 24ns for -15 part. * Changed of tOH from 3ns to 2.5ns. * Changed of tSS from 2.5ns to 2.0ns for -75 part and from 3.0ns to 2.5ns for -1L part, from 4.0ns to 3.5ns for -15 part * Integration of VDDQ 1.8V device and 2.5V device. * Change VIH from 0.8xVDDQ to 0.9xVDDQ and VOH from 0.9xVDDQ to 0.95xVDDQ. * Integration of PASR part anf TCSR part.
Revision 0.4 (December 3. 2001, Final)
* Final specification.
Rev. 0.4 Dec. 2001
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
K4S56163LC-RF(R)
4M x 16Bit x 4 Banks Mobile SDRAM in 54CSP
FEATURES
* JEDEC standard 2.5V power supply. * LVCMOS compatible with multiplexed address. * Four banks operation. * MRS cycle with address key programs. -. CAS latency (1 & 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). * EMRS cycle with address key programs. * All inputs are sampled at the positive going edge of the system clock. * Special Function Support. -. PASR (Partial Array Self Refresh). -. TCSR (Temperature Compensated Self Refresh). * DQM for masking. * Auto refresh. * 64ms refresh period (8K cycle). * Commercial Temperature Operation (-25C ~ 70 C).
CMOS SDRAM
GENERAL DESCRIPTION
The K4S56163LC is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
ORDERING INFORMATION
Max Freq. Interface Package 133MHz(CL=3) K4S56163LC-RF/R75 100MHz(CL=2) LVCMOS 54 CSP K4S56163LC-RF/R1L 100MHz(CL=3)*1 K4S56163LC-RF/R15 66MHz(CL=2/3)*2 -RR ; Super Low Power, Commercial Temperature. -RF ; Low Power, Commercial Temperature. Note : 1. In case of 40MHz Frequency, CL1 can be supported. 2. In case of 33MHz Frequency, CL1 can be supported. Part No.
FUNCTIONAL BLOCK DIAGRAM
I/O Control LWE
Data Input Register
LDQM
Bank Select 4M x 16 4M x 16 4M x 16 4M x 16
Refresh Counter
Output Buffer
Row Decoder
Sense AMP
Row Buffer
DQi
Address Register
CLK ADD
Column Decoder Col. Buffer
LRAS
LCBR
Latency & Burst Length
LCKE LRAS LCBR LWE LCAS
Programming Register LWCBR LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.4 Dec. 2001
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
K4S56163LC-RF(R)
Package Dimension and Pin Configuration
< Bottom View*1 >
E1
CMOS SDRAM
< Top View*2 >
54Ball(6x9) CSP 1 2 DQ15 DQ13 DQ11 DQ9 NC CLK A11 A7 A5 3 VSSQ VDDQ VSSQ VDDQ VSS CKE A9 A6 A4 7 VDDQ VSSQ VDDQ VSSQ VD D CAS BA0 A0 A3 8 DQ0 DQ2 DQ4 DQ6 LDQM RAS BA1 A1 A2 9 VD D DQ1 DQ3 DQ5 DQ7 WE CS A10 VD D
9 A B C D1 D E F G H J
8
7
6
5
4
3
2
1 e
A B C D E F G H J
D/2 D
VSS DQ14 DQ12 DQ10 DQ8 UDQM A12 A8 VSS
E E/2
Pin Name CLK CS CKE A0 ~ A 12 BA0 ~ BA1 RAS
A A1
Pin Function System Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground
*2: Top View
CAS WE L(U)DQM D Q0 ~ 15 VDD /VSS VDDQ/VSSQ
Max. 0.20
Encapsulant
b
*1: Bottom View < Top View*2 >
#A1 Ball Origin Indicator
SAMSUNG
WEEK
K4S56163LC-R
[Unit:mm] Symbol A A1 E E1 D D1 e b Min 0.90 0.30 0.40 Typ 0.95 0.35 8.10 6.40 15.10 6.40 0.80 0.45 Max 1.00 0.40 0.50 0.08
Rev. 0.4 Dec. 2001
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
K4S56163LC-RF(R)
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on VD D supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD , VDDQ TSTG PD IOS Value -1.0 ~ 3.6 -1.0 ~ 3.6 -55 ~ +150 1 50
CMOS SDRAM
Unit V V C W mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, T = -25 to 70 C) A Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Symbol VD D VDDQ VIH VIL VOH VOL ILI Min 2.3 1.65 0.9 x V DDQ -0.3 0.95 x V DDQ -10 Typ 2.5 0 Max 2.7 2.7 VDDQ + 0.3 0.3 0.2 10 Unit V V V V V V uA 1 2 IOH = -0.1mA IOL = 0.1mA 3 Note
Note : 1. VIH (max) = 3.0V AC.The overshoot voltage duration is 3ns. 2. VIL (min) = -1.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. Dout is disabled, 0V VOUT VDDQ.
CAPACITANCE
Clock
(VDD = 2.5V, TA = 23C, f = 1MHz, V REF =0.9V 50 mV) Pin Symbol CCLK CIN CADD COUT Min 2.0 2.0 2.0 3.5 Max 4.0 4.0 4.0 6.0 Unit pF pF pF pF Note
RAS, CAS, WE, CS, CKE, DQM Address D Q0 ~ DQ15
Rev. 0.4 Dec. 2001
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
K4S56163LC-RF(R)
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 70C) Parameter Symbol Test Condition -75 Operating Current (One Bank Active) Precharge Standby Current in power-down mode ICC1 Burst length = 1 tRC tR C(min) IO = 0 mA CKE VIL(max), tCC = 10ns 75
CMOS SDRAM
Version -1L 70 -15 65
Unit
Note
mA
1
ICC2P
0.5 0.5 15
ICC2PS CKE & CLK VIL(max), tCC = ICC2N CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL (max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns
mA
Precharge Standby Current in non power-down mode ICC2NS Active Standby Current in power-down mode ICC3P
mA 10 6 6 25 mA
ICC3PS CKE & CLK VIL(max), tCC = ICC3N CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL (max), tCC = Input signals are stable IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs tRC tR C(min) TCSR Range 4 Banks -RF 2 Banks 1 Bank 4 Banks -RR 2 Banks 1 Bank
mA
Active Standby Current in non power-down mode (One Bank Active)
ICC3NS
25
mA
Operating Current (Burst Mode) Refresh Current
ICC4
115
95
85
mA
1
ICC5
165 -25~45C 500 400 350 360 260 200
150
125 45~70C 750 550 420 630 430 300
mA C
2
3 uA 4
Self Refresh Current
ICC6
CKE 0.2V
Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S56163LC-RF** 4. K4S56163LC-RR** 5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)
Rev. 0.4 Dec. 2001
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
K4S56163LC-RF(R)
AC OPERATING TEST CONDITIONS
Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition
VDDQ
CMOS SDRAM
(VDD = 2.5V 0.2V, TA = -25 to 70C ) Value 0.95 x V DDQ / 0.2 0.5 x VDDQ tr/tf = 1/1 0.5 x VDDQ See Fig. 2
Vtt=0.5 x VDDQ
Unit V V ns V
500 Output 500 VOH (DC) = 0.95 x V DDQ, IOH = -0.1mA Output VOL (DC) = 0.2V, IOL = 0.1mA 30pF Z0=50
50
30pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Symbol - 75 tRRD (min) tRCD (min) tRP(min) tRAS(min) tRAS(max) tR C(min) tRDL(min) tDAL (min) tCDL(min) tBDL (min) tCCD (min) CAS latency=3 Number of valid output data CAS latency=2 CAS latency=1 65 15 20 20 45 Version -1L 20 24 24 60 100 84 2 2 CLK + tRP 1 1 1 2 1 0 ea 4 90 -15 30 30 30 60 ns ns ns ns us ns CLK CLK CLK CLK 2 2 3 1 2 1 1 1 1 Unit Note
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop.
Rev. 0.4 Dec. 2001
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
K4S56163LC-RF(R)
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter CAS latency=3 CLK cycle time CAS latency=2 CAS latency=1 CAS latency=3 CLK to valid output delay CAS latency=2 CAS latency=1 CAS latency=3 Output data hold time CAS latency=2 CAS latency=1 CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CAS latency=3 CLK to output in Hi-Z CAS latency=2 CAS latency=1 tSHZ tC H tC L tSS tSH tSLZ tOH 2.5 2.5 2.5 2.5 2.0 1.0 1 5.4 7 tSAC tC C Symbol Min 7.5 10 5.4 7 2.5 2.5 2.5 3 3 2.5 1.5 1 7 8 20 1000 - 75 Max Min 10 12 25 7 8 20 2.5 2.5 2.5 3.5 3.5 3.5 2.0 1 1000 -1L Max Min 15 15 30 - 15
CMOS SDRAM
Unit Max
Note
1000
ns
1
9 9 24 ns 1,2
ns
2
ns ns ns ns ns 9 9 24 ns
3 3 3 3 2
Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev. 0.4 Dec. 2001
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
K4S56163LC-RF(R)
SIMPLIFIED TRUTH TABLE
COMMAND Register Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit
CKEn-1 CKEn CS RAS CAS WE DQM BA0,1
CMOS SDRAM
A10 /AP A11, A12, A9 ~ A 0 Note
H H
X H L H X X
L L L H L L
L L H X L H
L L H X H L
L H H X H H
X X
OP CODE X
1, 2 3 3 3 3
L H H
X X X V V
X Row Address L H L
Column Address (A0~ A8) Column Address (A0~ A8)
Bank Active & Row Addr. Read & Column Address Write & Column Address Burst Stop Precharge Bank Selection All Banks Entry Exit Entry Precharge Power Down Mode Exit DQM No Operation Command Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable
4 4, 5 4 4, 5 6
H H H
X X X
L L L H L X H L H L
H H L X V X X H X V X
L H H X V X X H X V
L L L X V X X H X V
X X X
V
H X
V X
L H
X
Clock Suspend or Active Power Down
H L H
L H L
X X X
X
X X V X X 7
L H H
H
X
H L
X H
X H
X H
X
(V=Valid, X=Dont Care, H=Logic High, L=Logic Low) Notes : 1. OP Code : Operand Code A0 ~ A 12 & BA0 ~ BA1 : Program keys. (@MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are the same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. Partial self refresh can be issued only after setting partial self refresh mode. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A 10 /AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency is 0), but in read operation makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
Rev. 0.4 Dec. 2001
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
DEVICE OPERATIONS
A. MODE REGISTER FIELD TABLE TO PROGRAM MODES
CMOS SDRAM
Register Programmed with Normal MRS
Address Function BA0 ~ BA1*1 "0" Setting for Normal MRS A12 ~ A10/AP RFU A9 *2 W.B.L A8 A7 A6 A5 CAS Latency A4 A3 BT A2 A1 Burst Length A0
Test Mode
Normal MRS Mode
Test Mode A8 0 0 1 1 A7 0 1 0 1 Type Mode Register Set Reserved Reserved Reserved A6 0 0 0 0 1 1 1 1 CAS Latency A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserved 1 2 3 Reserved Reserved Reserved Reserved 0 0 Setting for Normal MRS BA1 A3 0 1 Burst Type Type Sequential Interleave Mode Select BA0 Mode A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 Burst Length A0 0 1 0 1 0 1 0 1 BT=0 1 2 4 8 BT=1 1 2 4 8
Write Burst Length A9 0 1 Length Burst Single Bit
Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved
Full Page Length : 256(x16)
Register Programmed with Extended MRS
Address Function BA1 BA0 A12 ~ A10/AP A9 A8 RFU A7 A6 A5 A4 A3 A2 A1 PASR A0 Mode Select TCSR
Extended MRS for PASR & TCSR
Mode Select BA1 0 0 1 1 BA0 0 1 0 1 Mode Normal MRS Reserved Extended MRS for Mobile DRAM Reserved Reserved Address A12 ~ A10/AP 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 0 1 1 A3 0 1 0 1 TCSR Temperature 45 C ~ 70 C 15 C ~ 45 C -25 C ~ 15 C 70 C ~ 85 C A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 PASR *3, 4 A0 0 1 0 1 0 1 0 1 # of Banks 4 Banks(All Banks) 2 Banks(1/2 of All Banks) 1 Bank(1/4 of All Banks) Reserved Reserved Reserved Reserved Reserved
Notes : 1.RFU(Reserved for future use) should stay "0" during MRS cycle. 2.In case of 64M Partial Self Refresh, one bank(BA1=BA0=0) is selected. In case of 128M Partial Self Refresh, two banks(BA1=0) are selected. 3.Mobile DRAM supports PASR of all banks(256Mb), 1/2 of all banks(128Mb) and 1/4 of all banks(64Mb).
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
DEVICE OPERATIONS
Partial Array Self Refresh
CMOS SDRAM
1. In order to save power consumption, Mobile DRAM has PASR option. 2. Mobile DRAM supports 3 kinds of PASR in self refresh mode ; 4 Banks(256Mb), 2 Banks(128Mb) and 1 Bank(64Mb).
Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Bank 1
Bank 2
Bank 3
Bank 2
Bank 3
Bank 2
Bank 3
- 4 Banks
- 2 Banks
- 1 Bank
Partial Self Refresh Area
Temperature Compensated Self Refresh
1. In order to save power consumption, Mobile DRAM has TCSR option. 2. Mobile DRAM supports 2 kinds of TCSR range by EMRS setting. ; 45 C ~ 70 C, -25 C ~ 45 C.
MRS Address A4
0 1 0 1
Self Refresh Current (Icc6) Temperature Range
45 C ~ 70 C 70 C ~ 85 C 15 C ~ 45 C -25 C ~ 15 C 4 Banks -RF -RR 630 N/A 360 2 Banks -RF 550 N/A 400 -RR 430 N/A 260 1 Bank -RF 420 N/A 350 -RR 300 N/A 200 uA
Unit
A3
0 1 1 0
750 N/A 500
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
DEVICE OPERATIONS
C. BURST SEQUENCE 1. BURST LENGTH = 4
Initial Address A1 A0 0 0 0 1 1 1 0 1 Sequential 0 1 2 3 1 2 3 0 2 3 0 1 3 0 1 2 0 1 2 3 1 0 3 2
CMOS SDRAM
Interleave 2 3 0 1 3 2 1 0
2. BURST LENGTH = 8
A2 0 0 0 0 1 1 1 1 Initial Address A1 A0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 Sequential 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 Interleave 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
DEVICE OPERATIONS
D. DEVICE OPERATIONS
ADDRESSES of 64Mb BANK ADDRESSES (BA0 ~ BA1)
: In case x 4
This SDRAM is organized as four independent banks of 4,194,304 words x 4 bits memory arrays. The BA0 ~ BA1 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank addresses BA0 ~ BA1 are latched at bank active, read, write, mode register set and precharge operations.
CMOS SDRAM
ADDRESSES of 128Mb
BANK ADDRESSES (BA0 ~ BA1) : In case x 4
This SDRAM is organized as four independent banks of 8,388,608 words x 4 bits memory arrays. The BA 0 ~ BA1 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank addresses BA0 ~ BA1 are latched at bank active, read, write, mode register set and precharge operations.
: In case x 8
This SDRAM is organized as four independent banks of 2,097,152 words x 8 bits memory arrays. The BA0 ~ BA1 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank addresses BA0 ~ BA1 are latched at bank active, read, write, mode register set and precharge operations.
: In case x 8
This SDRAM is organized as four independent banks of 4,194,304 words x 8 bits memory arrays. The BA 0 ~ BA1 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank addresses BA0 ~ BA1 are latched at bank active, read, write, mode register set and precharge operations.
: In case x 16
This SDRAM is organized as four independent banks of 1,048,576 words x 16 bits memory arrays. The BA 0 ~ BA1 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank addresses BA0 ~ BA1 are latched at bank active, read, write, mode register set and precharge operations.
: In case x 16
This SDRAM is organized as four independent banks of 2,097,152 words x 16 bits memory arrays. The BA 0 ~ BA1 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank addresses BA0 ~ BA1 are latched at bank active, read, write, mode register set and precharge operations.
ADDRESS INPUTS (A0 ~ A11)
: In case x 4
The 22 address bits are required to decode the 4,194,304 word locations are multiplexed into 12 address input pins (A0 ~ A11). The 12 bit row addresses are latched along with RAS and BA0 ~ BA1 during bank activate command. The 10 bit column addresses are latched along with CAS, WE and BA0 ~ BA1 during read or write command.
ADDRESS INPUTS (A0 ~ A11)
: In case x 4
The 23 address bits are required to decode the 8,388,608 word locations are multiplexed into 12 address input pins (A 0 ~ A11). The 12 bit row addresses are latched along with RAS and BA0 ~ BA1 during bank activate command. The 11 bit column addresses are latched along with CAS, WE and BA0 ~ BA1 during read or write command.
: In case x 8
The 21 address bits are required to decode the 2,097,152 word locations are multiplexed into 12 address input pins (A0 ~ A11). The 12 bit row addresses are latched along with RAS and BA0 ~ BA1 during bank activate command. The 9 bit column addresses are latched along with CAS, WE and BA0 ~ BA1 during read or write command.
: In case x 8
The 22 address bits are required to decode the 4,194,304 word locations are multiplexed into 12 address input pins (A 0 ~ A11). The 12 bit row addresses are latched along with RAS and BA0 ~ BA1 during bank activate command. The 10 bit column addresses are latched along with CAS, WE and BA0 ~ BA1 during read or write command.
: In case x 16
The 20 address bits are required to decode the 1,048,576 word locations are multiplexed into 12 address input pins (A0 ~ A11). The 12 bit row addresses are latched along with RAS and BA0 ~ BA1 during bank activate command. The 8 bit column addresses are latched along with CAS, WE and BA0 ~ BA1 during read or write command.
: In case x 16
The 21 address bits are required to decode the 2,097,152 word locations are multiplexed into 12 address input pins (A 0 ~ A11). The 12 bit row addresses are latched along with RAS and BA0 ~ BA1 during bank activate command. The 9 bit column addresses are latched along with CAS, WE and BA0 ~ BA1 during read or write command.
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
DEVICE OPERATIONS
D. DEVICE OPERATIONS (continued)
ADDRESSES of 256Mb
BANK ADDRESSES (BA0 ~ BA1) : In case x 4
This SDRAM is organized as four independent banks of 16,777,216 words x 4 bits memory arrays. The BA 0 ~ BA1 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank addresses BA0 ~ BA1 are latched at bank active, read, write, mode register set and precharge operations.
CMOS SDRAM
CLOCK (CLK)
The clock input is used as the reference for all SDRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between V IL and VIH. During operation with CKE high all inputs are assumed to be in a valid state (low or high) for the duration of set-up and hold time around positive edge of the clock in order to function well Q perform and IC C specifications.
: In case x 8
This SDRAM is organized as four independent banks of 8,388,608 words x 8 bits memory arrays. The BA0 ~ BA1 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank addresses BA0 ~ BA1 are latched at bank active, read, write, mode register set and precharge operations.
CLOCK ENABLE (CKE)
The clock enable(CKE) gates the clock onto SDRAM. If CKE goes low synchronously with clock (set-up and hold time are the same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When all banks are in the idle state and CKE goes low synchronously with clock, the SDRAM enters the power down mode from the next clock cycle. The SDRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least "1CLK + tSS" before the high going edge of the clock,
: In case x 16
This SDRAM is organized as four independent banks of 4,194,304 words x 16 bits memory arrays. The BA 0 ~ BA1 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank addresses BA0 ~ BA1 are latched at bank active, read, write, mode register set and precharge operations.
ADDRESS INPUTS (A0 ~ A12)
: In case x 4
The 24 address bits are required to decode the 16,777,216 word locations are multiplexed into 13 address input pins (A0 ~ A12). The 13 bit row addresses are latched along with RAS and BA0 ~ BA1 during bank activate command. The 11 bit column addresses are latched along with CAS, WE and BA0 ~ BA1 during read or write command.
then the SDRAM becomes active from the same clock edge accepting all the input commands.
NOP and DEVICE DESELECT
When RAS, CAS and WE are high, the SDRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS, CAS, WE and all the address inputs are ignored.
: In case x 8
The 23 address bits are required to decode the 8,388,608 word locations are multiplexed into 13 address input pins (A0 ~ A12). The 13 bit row addresses are latched along with RAS and BA0 ~ BA1 during bank activate command. The 10 bit column addresses are latched along with CAS, WE and BA0 ~ BA1 during read or write command.
: In case x 16
The 22 address bits are required to decode the 4,194,304 word locations are multiplexed into 13 address input pins (A0 ~ A 12). The 13 bit row addresses are latched along with RAS and BA0 ~ BA1 during bank activate command. The 9 bit column addresses are latched along with CAS, WE and BA0 ~ BA1 during read or write command.
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
DEVICE OPERATIONS
D. DEVICE OPERATIONS (continued)
DQM OPERATION
The DQM is used to mask input and output operations. It works similar to OE during read operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock. The DQM signal is important during burst interruptions of write with read or precharge in the SDRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid unwanted or incomplete writes when the complete burst write is not required. Please refer to DQM timing diagram also.
CMOS SDRAM
EXTENDED MODE REGISTER SET (EMRS)
The extended mode register stores the data for selecting partial self refresh or temperature compensated self refresh. EMRS cycle is not mandatory and the EMRS command needs to be issued only when either PASR or TCSR is used. The default state without EMRS command issued is +85C and all 4 banks refreshed. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA1 ,low on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0 ~ A11 in the same cycle as CS, RAS, CAS and WE going low is written in the extended mode register. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 - A2 are used for partila self refresh and A3 - A4 are used for Temprature compensated self refresh. "Low" on BA1 and "High" on BA0 are used for EMRS. All the other address pins except A0,A1,A2, BA1, BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the various operating modes of SDRAM. It programs the CAS latency, burst type, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SDRAM. The mode register is written by asserting low on CS, RAS, CAS and WE (The SDRAM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0 ~ An and BA0 ~ BA1 in the same cycle as CS, RAS, CAS and WE going low is the data written in the mode register. Two clock cycles is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on the fields of functions. The burst length field uses A0 ~ A2, burst type uses A CAS 3, latency (read latency from column address) use A4 ~ A6, vendor specific options or test mode use A7 ~ A8, A10/AP ~ A n and BA0 ~ BA1. The write burst length is programmed using A 9. A7 ~ A 8, A10/ AP ~ An and BA0 ~ BA1 must be set to low for normal SDRAM operation. Refer to the table for specific codes for various burst length, burst type and CAS latencies.
BANK ACTIVATE.
The bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with desired row and bank address, a row access is initiated. The read or write operation can occur after a time delay of t C D(min) from the time of R bank activation. tRCD is an internal timing parameter of SDRAM, therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing tRCD (min) with cycle time of the clock and then rounding off the result to the next higher integer.
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
DEVICE OPERATIONS
D. DEVICE OPERATIONS (continued)
The SDRAM has four internal banks in the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of four banks simultaneously. Also the noise generated during sensing of each bank of SDRAM is high, requiring some time for power supplies to recover before another bank can be sensed reliably. t R D(min) specifies the minimum R time required between activating different bank. The number of clock cycles required between different bank activation must be calculated similar to tRCD specification. The minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by t AS(min). R Every SDRAM bank activate command must satisfy t AS(min) R specification before a precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by tRAS(max). The number of cycles for both tRAS(min) and tRAS(max) can be calculated similar to t RCD specification.
CMOS SDRAM
BURST WRITE
The burst write command is similar to burst read command and is used to write data into the SDRAM on consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on CS, CAS and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing can be completed yet. The writing can be completed by issuing a burst read and DQM for blocking data inputs or burst write in the same or another active bank. The burst stop command is valid at every burst length. The write burst can also be terminated by using DQM for blocking data and procreating the bank tRDL after the last data input to be written into the active row. See DQM OPERATION also.
BURST READ
The burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The burst read command is issued by asserting low on CS and CAS with WE being high on the positive edge of the clock. The bank must be active for at least tRCD (min) before the burst read command is issued. The first output appears in CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of the burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid at every page burst length.
ALL BANKS PRECHARGE
All banks can be precharged at the same time by using Precharge all command. Asserting low on CS, RAS, and WE with high on A10/AP after all banks have satisfied tRAS(min) requirement, performs precharge on all banks. At the end of tRP after performing precharge to all the banks, all banks are in idle state.
PRECHARGE
The precharge operation is performed on an active bank by asserting low on CS, RAS, WE and A10/AP with valid BA0 ~ BA1 of the bank to be precharged. The precharge command can be asserted anytime after tRAS (min) is satisfied from the bank active command in the desired bank. R P is defined as the minimum t number of clock cycles required to complete row precharge is calculated by dividing tR P with clock cycle time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by t AS (max). Therefore, each bank R activate command. At the end of precharge, the bank enters the idle state and is ready to be activated again. Entry to Power down, Auto refresh, Self refresh and Mode register set etc. is possible only when all banks are in idle state.
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
DEVICE OPERATIONS
D. DEVICE OPERATIONS (continued)
AUTO PRECHARGE
The precharge operation can also be performed by using auto precharge. The SDRAM internally generates the timing to satisfy tRAS(min) and "t RP" for the programmed burst length and CAS latency. The auto precharge command is issued at the same time as burst read or burst write by asserting high on A10/AP. If burst read or burst write by asserting high on A10/AP, the bank is left active until a new command is asserted. Once auto precharge command is given, no new commands are possible to that particular bank until the bank achieves idle state.
CMOS SDRAM
SELF REFRESH
The self refresh is another refresh mode available in the SDRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SDRAM. In self refresh mode, the SDRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing are internally generated to reduce power consumption. The self refresh mode is entered from all banks idle state by asserting low on CS, RAS, CAS and CKE with high on WE. Once the self refresh mode is entered, only CKE state being low matters, all the other inputs including the clock are ignored in order to
AUTO REFRESH
The storage cells of 64Mb, 128Mb and 256Mb SDRAM need to be refreshed every 64ms to maintain data. An auto refresh cycle
remain in the self refresh mode. The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP's for a minimum time of tRC before the SDRAM reaches idle state to begin normal operation. If the system uses burst auto refresh during normal operation, it is recommended to use burst 8192 auto refresh cycles for 256Mb and burst 4096 auto refresh cycles for 128Mb and 64Mb immediately after exiting in self refresh mode.
accomplishes refresh of a single row of storage cells. The internal counter increments automatically on every auto refresh cycle to refresh all the rows. An auto refresh command is issued by
asserting low on CS, RAS and CAS with high on CKE and WE. The auto refresh command can only be asserted with both banks being in idle state and the device is not in power down mode (CKE is high in the previous cycle). The time required to complete the auto refresh operation is specified by t RC (min). The minimum number of clock cycles required can be calculated by driving tRC with clock cycle time and them rounding up to the next higher integer. The auto refresh command must be followed by NOP's until the auto refresh operation is completed. All banks will be in the idle state at the end of auto refresh operation. The auto refresh is the preferred refresh mode when the SDRAM is being used for normal data transactions. The 64Mb and 128Mb SDRAM's auto refresh cycle can be performed once in 15.6us or a burst of 4096 auto refresh cycles once in 64ms. The 256Mb SDRAM's auto refresh cycle can be performed once in 7.8us or a burst of 8192 auto refresh cycles once in 64ms.
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
DEVICE OPERATIONS
E. BASIC FEATURE AND FUNCTION DESCRIPTIONS
CMOS SDRAM
1. CLOCK Suspend
1) Clock Suspended During Write (BL=4) CLK CMD CKE
Masked by CKE
2) Clock Suspended During Read (BL=4) CLK
WR
CMD CKE
RD
Masked by CKE
Internal CLK DQ(CL2) DQ(CL3) D0 D0 D1 D1 D2 D2 Not Written D3 D3
Internal CLK DQ(CL2) DQ(CL3) Q0 D0 Q1 Q0 Q2 Q1 Q3 Q2 Q3
Suspended Dout
2. DQM Operation
1) Write Mask (BL=4) CLK CMD DQM
Masked byDQM
2) Read Mask (BL=4) CLK
WR
CMD DQM DQ(CL2) DQ(CL3)
RD
DQ(CL2) DQ(CL3)
D0 D0
D1 D1
D3 D3
Q0
Masked by DQM Hi-Z
Q2 Q1
Q3 Q2
Hi-Z
Q3
DQM to Data-in Mask = 0
DQM to Data-out Mask = 2
3) DQM with Clock Suspended (Full Page Read) CLK CMD CKE DQM DQ(CL2) DQ(CL3) Q0
Hi-Z Hi-Z
*2
RD
Q2 Q1
Hi-Z Hi-Z
Hi-Z
Q4 Q3
Hi-Z
Q6 Q5
Q7 Q6
Q8 Q7
*Note : 1. CKE to CLK disable/enable = 1CLK. 2. DQM makes data out Hi-Z after 2CLKs which should masked by CKE " L" 3. DQM masks both data-in and data-out.
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
DEVICE OPERATIONS
3. CAS Interrupt (I)
CMOS SDRAM
1) Read interrupted by Read (BL=4) CLK CMD ADD DQ(CL2) DQ(CL3)
tCCD *2
*1
RD A
RD B QA0 QB0 QA0 QB1 QB0 QB2 QB1 QB3 QB2 QB3
2) Write interrupted by Write (BL=2) CLK CMD WR WR
3) Write interrupted by Read (BL=2) CLK CMD WR RD
tCCD * 2
tCCD * 2
ADD DQ
A DA0
B DB0 DB1
ADD DQ(CL2) DQ(CL3)
A DA0 DA0
B QB0 QB1 QB0 QB1
tCDL *3
tCDL *3
*Note : 1. By " Interrupt", It is meant to stop burst read/write by external command before the end of burst. By "CAS Interrupt", to stop burst read/write by CAS access ; read and write. 2. tCCD : CAS to CAS delay. (=1CLK) 3. tCDL : Last data in to new column address delay. (=1CLK)
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
DEVICE OPERATIONS
4. CAS Interrupt (II) : Read Interrupted by Write & DQM
(a) CL=2, BL=4 CLK i) CMD DQM DQ ii) CMD DQM DQ iii) CMD DQM DQ iv) CMD DQM DQ (b) CL=3, BL=4 CLK i) CMD DQM DQ ii) CMD DQM DQ iii) CMD DQM DQ iii) CMD DQM DQ iv) CMD DQM DQ Q0
Hi-Z
*1
CMOS SDRAM
RD
WR
D0 RD
D1 WR
D2
D3
Hi-Z
D0
D1 WR
D2
D3
RD
Hi-Z
D0
D1 WR
D2
D3
RD
Q0
Hi-Z
*1
D0
D1
D2
D3
RD
WR
D0 RD
D1 WR
D2
D3
D0 RD
D1 WR
D2
D3
D0 RD
D1 WR
D2
D3
Hi-Z
D0
D1 WR
D2
D3
RD
D0
D1
D2
D3
*Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
DEVICE OPERATIONS
5. Write Interrupted by Precharge & DQM
1) tRDL = 1 CLK CLK
*3
CMOS SDRAM
2) tRDL = 2CLK CLK
*3
CMD DQM DQ
WR
PRE
*2
CMD DQM
WR
PRE
*2
D0
D1
D2
Masked by DQM
DQ
D0
D1
D2
Masked by DQM
*Note : 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out. 2. To inhibit invalid write, DQM should be issued. 3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of four banks operation.
6. Precharge
1) Normal Write BL=4 & tRDL=1CLK CLK CMD DQ WR D0 D1 D2 D3
tRDL * 1
BL=4 & tRDL=2CLK CLK CMD DQ WR D0 D1 D2 D3
tRDL *1
PRE
PRE
2) Normal Read (BL=4) CLK
*2
CMD DQ(CL2) DQ(CL3)
RD Q0 Q1 Q0
PRE Q2 Q1 Q3 Q2
1
Q3
2
7. Auto Precharge
1) Normal Write (BL=4) CLK CMD DQ WR D0 D1 D2 D3
tRDL =1CLK
2) Normal Read (BL=4) CLK ACT CMD DQ(CL2) ACT DQ(CL3) RD Q0 Q1 Q0 Q2 Q1 Q3 Q2 Q3
CMD DQ
WR D0 D1 D2 D3
tDAL =1CLK +20ns*4
Auto Precharge Starts * 3 tRDL =2CLK tDAL =2CLK +20ns * 4 Auto Precharge Starts @tRDL=1CLK *3 Auto Precharge Starts@tRDL=2CLK *3
*Note : 1. SAMSUNG can support tRDL=1CLK and tRDL=2CLK for all memory devices. SAMSUNG recommends tRDL=2 CLK. 2. Number of valid output data after row precharge : 1, 2 for CAS Latency = 2, 3 respectively. 3. The row active command of the precharge bank can be issued after tR P from this point. The new read/write command of other activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same bank is illegal 4. tDAL defined Last data in to Active delay. SAMSUNG can support tDAL=1CLK+20ns and 2CLK+20ns ,recommends tDAL=2CLK+20ns.
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
DEVICE OPERATIONS
8. Burst Stop & Interrupted by Precharge
1) Normal Write BL=4 & tRDL=1CLK CLK CMD DQM DQ D0 D1 D2
tRDL*1
CMOS SDRAM
BL=4 & tRDL=2CLK CLK
WR
PRE
CMD DQM DQ
WR
PRE
D0
D1
D2
tRDL*1
2) Write Burst Stop (BL=8) CLK CMD DQM DQ D0 D1 D2 D3
tBDL *2
3) Read Interrupted by Precharge (BL=4) CLK
WR
STOP
CMD DQ(CL2) DQ(CL3)
RD
PRE
1
Q0
Q1 Q0 Q1
2
4) Read Burst Stop (BL=4) CLK CMD DQ(CL2) DQ(CL3) RD
STOP
1
Q0
Q1 Q0
2
Q1
9. MRS
1) Mode Register Set CLK
*4
CMD
PRE
tRP
MRS
2CLK
ACT
*Note : 1. SAMSUNG can support t RDL=1CLK and tRDL=2CLK for all memory devices. SAMSUNG recommends tRDL=2 CLK. 2. tBDL : 1 CLK ; Last data in to burst stop delay. Read or write burst stop command is valid at every burst length. 3. Number of valid output data after row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectively. 4. PRE : All banks precharge is necessary. MRS can be issued only at all banks precharge state.
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
DEVICE OPERATIONS
10. Clock Suspend Exit & Power Down Exit
1) Clock Suspend (=Active Power Down) Exit CLK CKE
tSS
CMOS SDRAM
2) Power Down (=Precharge Power Down) Exit CLK CKE Internal CLK RD CMD
*2
tSS
Internal CLK CMD
*1
NOP ACT
11. Auto Refresh & Self Refresh
1) Auto Refresh CLK
*4
~ ~
*5
CMD CKE
PRE
AR ~ ~
CMD
tRP
tRC
2) Self Refresh CLK
Note 6
*4
CMD CKE
PRE
SR
~ ~
~ ~
~~ ~~
CMD
~ ~
tRP
~ ~
tRC
*Note : 1. Active power down : one or more banks active state. 2. Precharge power down : all banks precharge state. 3. The auto refresh is the same as CBR refresh of conventional DRAM. No precharge commands are required after auto refresh command. During tRC from auto refresh command, any other command can not be accepted. 4. Before executing auto/self refresh command, all banks must be idle state. 5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry. 6. During self refresh mode, refresh interval and refresh operation are performed internally. After self refresh entry, self refresh mode is kept while CKE is low. During self refresh mode, all inputs except CKE will be don't cared, and outputs will be in Hi-Z state. For the time interval of tRC from self refresh exit command, any other command can not be accepted. Before/After self refresh mode, burst auto refresh cycle (4096 cycles for 64Mb & 128Mb, 8192 cycles for 256Mb) is recommended.
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
DEVICE OPERATIONS
12. About Burst Type Control
Basic MODE Sequential Counting Interleave Counting Random column Access t CCD = 1 CLK
CMOS SDRAM
At MRS A3 = "0". See the BURST SEQUENCE TABLE. (BL=4, 8) BL=1, 2, 4, 8 and full page. At MRS A3 = "1". See the BURST SEQUENCE TABLE. (BL=4, 8) BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting Every cycle Read/Write Command with random column address can realize Random Column Access. That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
Random MODE
13. About Burst Length Control
1 2 Basic MODE 4 8 Full Page Special MODE Random MODE At MRS A2,1,0 = "000". At auto precharge, tRAS should not be violated. At MRS A2,1,0 = "001". At auto precharge, tRAS should not be violated. At MRS A2,1,0 = "010". At MRS A2,1,0 = "011". At MRS A2,1,0 = "111". Wrap around mode(infinite burst length) should be stopped by burst stop. RAS interrupt or CAS interrupt At MRS A9 = "1". Read burst =1, 2, 4, 8, full page write Burst =1 At auto precharge of write, t RAS should not be violated. tBDL = 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively Using burst stop command, any burst length control is possible. Before the end of burst, Row precharge command of the same bank stops read/write burst with Row precharge. tRDL= 2 with DQM, valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively. During read/write burst with auto precharge, RAS interrupt can not be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst. During read/write burst with auto precharge, CAS interrupt can not be issued.
BRSW Burst Stop
Interrupt MODE
RAS Interrupt (Interrupted by Precharge)
CAS Interrupt
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
DEVICE OPERATIONS
FUNCTION TRUTH TABLE (TABLE 1)
Current State CS H L L IDLE L L L L L H L L Row Active L L L L L H L L Read L L L L L H L L Write L L L L L H L Read with Auto Precharge L L L L H L Write with Auto Precharge L L L L H L Precharging L L L L RAS X H H H L L L L X H H H H L L L X H H H H L L L X H H H H L L L X H H H L L X H H H L L X H H H L L CAS X H H L H H L L X H H L L H H L X H H L L H H L X H H L L H H L X H H L H L X H H L H L X H H L H H WE X H L X H L H L X H L H L H L X X H L H L H L X X H L H L H L X X H L X X X X H L X X X X H L X H L BA X X X BA BA BA X OP code X X X BA BA BA BA X X X X BA BA BA BA X X X X BA BA BA BA X X X X BA BA X X X X BA BA X X X X BA BA BA ADDR X X X CA, A1 0/AP RA A1 0/AP X OP code X X X CA, A1 0/AP CA, A1 0/AP RA A1 0/AP X X X X CA, A1 0/AP CA, A1 0/AP RA A1 0/AP X X X X CA, A1 0/AP CA, A1 0/AP RA A1 0/AP X X X X CA, A1 0/AP RA, RA10 X X X X CA, A1 0/AP RA, RA10 X X X X CA RA A1 0/AP NOP NOP ILLEGAL ILLEGAL Row (& Bank) Active ; Latch RA NOP Auto Refresh or Self Refresh Mode Register Access NOP NOP ILLEGAL ACTION
CMOS SDRAM
Note
2 2 4 5 5
2
Begin Read ; latch CA ; determine AP Begin Write ; latch CA ; determine AP ILLEGAL Precharge ILLEGAL NOP (Continue Burst to End --> Row Active) NOP (Continue Burst to End --> Row Active) Term burst --> Row active Term burst, New Read, Determine AP Term burst, New Write, Determine AP ILLEGAL Term burst, Precharge timing for Reads ILLEGAL NOP (Continue Burst to End --> Row Active) NOP (Continue Burst to End --> Row Active) Term burst --> Row active Term burst, New read, Determine AP Term burst, New Write, Determine AP ILLEGAL Term burst, precharge timing for Writes ILLEGAL NOP (Continue Burst to End --> Precharge) NOP (Continue Burst to End --> Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Continue Burst to End --> Precharge) NOP (Continue Burst to End --> Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP --> Idle after t R P NOP --> Idle after t R P ILLEGAL ILLEGAL ILLEGAL NOP --> Idle after t R P 2 2 2 4 2 2 3 3 2 3 3 2 2
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
DEVICE OPERATIONS
FUNCTION TRUTH TABLE (TABLE 1)
Current State CS L H L Row Activating L L L L L H L Refreshing L L L H Mode Register Accessing L L L L RAS L X H H H L L L X H H L L X H H H L CAS L X H H L H H L X H L H L X H H L X WE X X H L X H L X X X X X X X H L X X BA X X X X BA BA BA X X X X X X X X X X X ADDR X X X X CA RA A10 /AP X X X X X X X X X X X ILLEGAL NOP --> Row Active after tRCD NOP --> Row Active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP --> Idle after t R C NOP --> Idle after t R C ILLEGAL ILLEGAL ILLEGAL NOP --> Idle after 2 clocks NOP --> Idle after 2 clocks ILLEGAL ILLEGAL ILLEGAL ACTION
CMOS SDRAM
Note
2 2 2 2
Abbreviations : RA = Row Address NOP = No Operation Command
BA = Bank Address CA = Column Address
AP = Auto Precharge
*Note : 1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle. 2. Illegal to bank in specified state ; Function may be Iegal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and A10/AP). 5. Illegal if any bank is not idle.
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
DEVICE OPERATIONS
FUNCTION TRUTH TABLE (TABLE 2)
Current State CKE (n-1) H L Self Refresh L L L L L H All Banks Precharge Power Down L L L L L L H H H H All Banks Idle H H H H L Any State other than Listed above H H L L CKE n X H H H H H L X H H H H H L H L L L L L L L L H L H L CS X H L L L L X X H L L L L X X H L L L L L L X X X X X RAS X X H H H L X X X H H H L X X X H H H L L L X X X X X CAS X X H H L X X X X H H L X X X X H H L H L L X X X X X WE X X H L X X X X X H L X X X X X H L X H H L X X X X X ADDR X X X X X X X X X X X X X X X X X X X RA X OP Code X X X X X INVALID ACTION
CMOS SDRAM
Note
Exit Self Refresh --> Idle after tRFC (ABI) Exit Self Refresh --> Idle after tRFC (ABI) ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Power Down --> ABI Exit Power Down --> ABI ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Low Power Mode) Refer to Table 1 Enter Power Down Enter Power Down ILLEGAL ILLEGAL Row (& Bank) Active Enter Self Refresh Mode Register Access NOP Refer to Operations in Table 1 Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend
6 6
7 7
8 8
8
9 9
Abbreviations : ABI = All Banks Idle, RA = Row Address *Note : 6. CKE low to high transition is asynchronous. 7. CKE low to high transition is asynchronous if restarts internal clock. A minimum setup time 1CLK + tSS must be satisfied before any command other than exit. 8. Power down and self refresh can be entered only from the both banks idle state. 9. Must be a legal command.
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
TIMING DIAGRAM
CMOS SDRAM
Single Bit Read - Write - Read Cycle(Same Page) @CAS Latency=3, Burst Length=1 Power Up Sequence Read & Write Cycle at Same Bank @Burst Length=4, tRDL=1CLK Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=1CLK Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK Page Read Cycle at Different Bank @Burst Length=4 Page Write Cycle at Different Bank @Burst Length=4, tRDL=1CLK Page Write Cycle at Different Bank @Burst Length=4, tRDL=2CLK Read & Write Cycle at Different Bank @Burst Length=4 Read & Write Cycle With Auto Precharge l @Burst Length=4 Read & Write Cycle With Auto Precharge ll @Burst Length=4 Clock Suspension & DQM Operation Cycle @CAS Letency=2, Burst Length=4 Read Interrupted by Precharge Command & Read Burst Stop Cycle @ Full Page Burst Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full Page Burst, tRDL=1CLK Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full Page Burst, tRDL=2CLK Active/precharge Power Dower Down Mode @CAS Latency=2 Burst Length=4 Self Refresh Entry & Exit Cycle & Exit Cycle Mode Register Set Cycle Auto Refresh Cycle
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
TIMING DIAGRAM
Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1
tCH
CMOS SDRAM
0 CLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
tCC
tCL HIGH
CKE
*Note 1
tRAS tRC
tSH
CS
tRCD tSH tSS tRP
RAS
tSS tCCD tSH
CAS
tSH tSS Ca Cb Cc Rb
ADDR
Ra tSS
*Note 2
*Note 2,3
*Note 2,3
*Note 2,3 *Note 4
*Note 2
BA0 ~ BA1
BS
BS
BS
BS
BS
BS
*Note 3
*Note 3
*Note 3 *Note 4
A10 /AP
Ra tRAC tSAC tSH Qa tSLZ tOH tSH Db tSS Qc
Rb
DQ
WE
tSS tSS tSH
DQM
Row Active
Read
Write
Read Precharge
Row Active
: Don't care
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
TIMING DIAGRAM
CMOS SDRAM
*Note : 1. All input except CKE & DQM can be don't care when CS is high at the CLK high going edge. 2. Bank active & read/write are controlled by BA0~BA1. 64Mb/128Mb BA0 BA1 0 0 0 1 1 0 1 1 256Mb BA0 BA1 0 0 1 0 0 1 1 1 Active & Read/Write Bank A Bank B Bank C Bank D
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command A10/AP 64Mb/128Mb BA0 BA1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 256Mb BA0 BA1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 Operation Disable auto precharge, leave bank A active at end of burst. Disable auto precharge, leave bank B active at end of burst. Disable auto precharge, leave bank C active at end of burst. Disable auto precharge, leave bank D active at end of burst. Enable auto precharge, precharge bank A at end of burst. Enable auto precharge, precharge bank B at end of burst. Enable auto precharge, precharge bank C at end of burst. Enable auto precharge, precharge bank D at end of burst.
0
1
4. A10/AP and BA0~BA1 control bank precharge when precharge command is asserted. A10/AP 0 0 0 0 1 64Mb/128Mb BA0 BA1 0 0 0 1 1 0 1 1 x x 256Mb BA0 BA1 0 0 1 0 0 1 1 1 x x Precharge Bank A Bank B Bank C Bank D All Banks
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
TIMING DIAGRAM
Power Up Sequence for Mobile DRAM
CMOS SDRAM
: Don't care
CLOCK
~~ ~~
CKE
~ ~
CS
~ ~
RAS
CAS
~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~
~~ ~~ ~~ ~~ ~~ ~~
~
~
~~
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
ADDR
Key
Key
RAa
BA0
BA1
A10/AP
RAa
DQ
~~ ~~
~ ~
Hi-Z
Hi-Z
WE
DQM
High level is necessary. tRP Precharge (All Bank) Auto Refresh
tRC Auto Refresh
~ ~
~
tRC Normal MRS Extended MRS Row Active (A-Bank)
1. Apply power and start clock, Attempt to maintain CKE= "H", DQM= "H" and the other pins are in NOP condition at the inputs. 2. Power is applied to VDD and VDDQ (simultaneously). 3. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 4. Issue precharge commands for all banks of the devices. 5. Issue 2 or more auto-refresh commands. 6. Issue a mode register set command to initialize the mode register. 7. Issue an extended mode register set command to define PASR or TCSR operating type of the device after normal MRS. EMRS cycle is not mandatory and EMRS command need to be issued only when either PASR or TCSR is used. The default state without EMRS command issued is +85C and all 4banks refreshed.
The device is now ready for the operation selected by EMRS. For operating with PASR or TCSR, set PASR or TCSR mode in EMRS setting stage. Adjustment to another mode in the state of PASR, TCSR or DS mode can be achieved by additional EMRS setting without asserting power up sequence again.
ELECTRONICS
~~
~
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
TIMING DIAGRAM
Read & Write Cycle at Same Bank @Burst Length=4, tRDL=1CLK
0 CLOCK CKE
tRC
CMOS SDRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
*Note 1
CS
tRCD
RAS
*Note 2
CAS ADDR BA0 BA1 A10 /AP
Ra Rb Ra Ca Rb Cb
tOH
CL=2
tRAC
Qa0
*Note 3
Qa1
Qa2
Qa3 tSHZ
*Note 4
Db0
Db1
Db2
Db3 tRDL
tSAC tOH
DQ CL=3
Qa0 tRAC
*Note 3
Qa1
Qa2
Qa3 tSHZ
*Note 4
Db0
Db1
Db2
Db3 tRDL
tSAC
WE
DQM
Row Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank)
Row Active (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
: Don't care
*Note :
1. Minimum row cycle times is required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z(t SHZ) after the clcok. 3. Access time from Row active command. tCC *(tRCD + CAS latency - 1) + tSAC 4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
TIMING DIAGRAM
Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK
0 CLOCK CKE
tRC
CMOS SDRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
*Note 1
CS
tRCD
RAS
*Note 2
CAS ADDR BA0 BA1 A10 /AP
Ra Rb Ra Ca Rb Cb
tOH
CL=2
tRAC
Qa0
*Note 3
Qa1
Qa2
Qa3 tSHZ
*Note 4
Db0
Db1
Db2
Db3 tRDL
tSAC tOH
DQ CL=3
Qa0 tRAC
*Note 3
Qa1
Qa2
Qa3 tSHZ
*Note 4
Db0
Db1
Db2
Db3 tRDL
tSAC
WE
DQM
Row Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank)
Row Active (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
: Don't care
*Note :
1. Minimum row cycle times is required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z(t SHZ) after the clcok. 3. Access time from Row active command. tCC *(tRCD + CAS latency - 1) + tSAC 4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
TIMING DIAGRAM
Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=1CLK
0 CLOCK CKE HIGH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMOS SDRAM
16
17
18
19
CS
tRCD
RAS
*Note 2
CAS
ADDR
Ra
Ca
Cb
Cc
Cd
Rb
BA0
BA1
A10 /AP
Ra tRDL
Rb
CL=2 DQ CL=3
Qa0
Qa1
Qb0
Qb1
Qb2
Dc0
Dc1
Dd0
Dd1 tDAL
*Note 4
Qa0
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd1
tCDL
WE
*Note 1 *Note 3
DQM
Row Active (A-Bank)
Read (A-Bank)
Read (A-Bank)
Write (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
Row Adiwe (A-Bank) : Don't care
*Note :
1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 4. tDAL, last data in to active delay, is 1CLK + 20ns
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
TIMING DIAGRAM
Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK
0 CLOCK CKE HIGH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMOS SDRAM
16
17
18
19
CS
tRCD
RAS
*Note 2
CAS
ADDR
Ra
Ca
Cb
Cc
Cd
Rb
BA0
BA1
A10 /AP
Ra tRDL
Rb
CL=2 DQ CL=3
Qa0
Qa1
Qb0
Qb1
Qb2
Dc0
Dc1
Dd0
Dd1 tDAL
*Note 4
Qa0
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd1
tCDL
WE
*Note 1 *Note 3
DQM
Row Active (A-Bank)
Read (A-Bank)
Read (A-Bank)
Write (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
Row Active (A-Bank) : Don't care
*Note :
1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 4. tDAL ,last data in to active delay, is 2CLK + 20ns.
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
TIMING DIAGRAM
Page Read Cycle at Different Bank @Burst Length=4
0 CLOCK CKE
*Note 1
CMOS SDRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
CS
RAS
*Note 2
CAS
ADDR
RAa
RBb
CAa
RCc
CBb
RDd
CCc
CDd
BA0
BA1
A10 /AP
RAa
RBb
RCc
RDd
CL=2 DQ CL=3
QAa0
QAa1
QAa2 QBb0
QBb1 QBb2
QCc0
QCc1
QCc2
QDd0 QDd1 QDd2
QAa0
QAa1
QAa2
QBb0
QBb1
QBb2 QCc0
QCc1
QCc2 QDd0
QDd1
QDd2
WE DQM
Row Active (A-Bank)
Read (A-Bank) Row Active (B-Bank)
Read (B-Bank) Row Acive (C-Bank)
Read (C-Bank) Row Active (D-Bank)
Read (D-Bank) Precharge (C-Bank)
Precharge (D-Bank)
Precharge (A-Bank)
Precharge (B-Bank) : Don't care
*Note :
1. CS can be don't cared when RAS, CAS and WE are high at the clock high going dege. 2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
TIMING DIAGRAM
Page Write Cycle at Different Bank @Burst Length=4, tRDL=1CLK
0 CLOCK CKE HIGH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMOS SDRAM
16
17
18
19
CS
RAS
*Note 2
CAS
ADDR
RAa
RBb CAa
CBb
RCc
RDd
CCc
CDd
BA0
BA1
A10/AP
RAa
RBb
RCc
RDd
DQ
DAa0
DAa1
DAa2
DAa3
DBb0 DBb1
DBb2 DBb3
DCc0
DCc1
DDd0
DDd1
DDd2
tCDL
tRDL
WE
*Note 1
DQM
Row Active (A-Bank)
Write (A-Bank) Row Active (B-Bank)
Write (B-Bank) Row Active (C-Bank)
Row Active (D-Bank) Write (C-Bank)
Write (D-Bank)
Precharge (All Banks)
: Don't care
*Note :
1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
TIMING DIAGRAM
Page Write Cycle at Different Bank @Burst Length=4, tRDL=2CLK
0 CLOCK CKE HIGH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMOS SDRAM
16
17
18
19
CS
RAS
*Note 2
CAS
ADDR
RAa
RBb CAa
CBb
RCc
RDd
CCc
CDd
BA0
BA1
A10/AP
RAa
RBb
RCc
RDd
DQ
DAa0
DAa1
DAa2
DAa3
DBb0 DBb1
DBb2 DBb3
DCc0
DCc1
DDd0
DDd1
DDd2
tCDL
tRDL
WE
*Note 1
DQM
Row Active (A-Bank)
Write (A-Bank) Row Active (B-Bank)
Write (B-Bank) Row Active (C-Bank)
Row Active (D-Bank) Write (C-Bank)
Write (D-Bank)
Precharge (All Banks)
: Don't care
*Note :
1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
TIMING DIAGRAM
Read & Write Cycle at Different Bank @Burst Length=4
0 CLOCK CKE HIGH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMOS SDRAM
16
17
18
19
CS RAS
CAS
ADDR
RAa
CAa
RDb
CDb RBc
CBc
BA0
BA1
A10 /AP
RAa
RDb
RBc tCDL
*Note 1
CL=2 DQ CL=3
QAa0 QAa1
QAa2
QAa3
DDb0
DDb1 DDb2 DDb3
QBc0
QBc1
QBc2
QAa0 QAa1
QAa2
QAa3
DDb0
DDb1 DDb2 DDb3
QBc0
QBc1
WE
DQM
Row Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank) Row Active (D-Bank)
Write (D-Bank) Row Active (B-Bank)
Read (B-Bank)
: Don't care
*Note :
1. tCDL should be met to complete write.
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
TIMING DIAGRAM
Read & Write Cycle with Auto Precharge I @Burst Length=4
0 CLOCK CKE HIGH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMOS SDRAM
16
17
18
19
CS
RAS
CAS
ADDR
RAa
RBb
CAa
CBb
RAc
CAc
BA0
BA1
A10 /AP
RAa
RBb
RAc
DQ
CL=2
QAa0 QAa1
QBb0
QBb1
QBb2 QBb3
DAc0
DAc1
CL=3
QAa0
QAa1
QBb0
QBb1 QBb2
QBb3
DAc0
DAc1
WE
DQM
Row Active (A-Bank)
Read with Auto Pre charge (A-Bank) Row Active (B-Bank)
Read without Auto precharge(B-Bank) Auto Precharge Start Point (A-Bank)* Note1
Precharge (B-Bank)
Row Active (A-Bank)
Write with Auto Precharge (A-Bank)
: Don't care *Note1: When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation. - if Read(Write) command without auto precharge is issued at B-Bank before A-Bank auto precharge starts, A-Bank auto precharge will start at B-Bank read command input point . - any command can not be issued at A-Bank during tRP after A-Bank auto precharge starts.
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
TIMING DIAGRAM
Read & Write Cycle with Auto Precharge II @Burst Length=4
0 CLOCK CKE HIGH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMOS SDRAM
16
17
18
19
CS
RAS
CAS
ADDR
Ra
Ca
Rb
Cb
BA0
BA1
A10 /AP
Ra
Rb
DQ
CL=2
Qa0
Qa1
Qa2
Qa3
Qb0
Qb1
Qb2
Qb3
CL=3
Qa0
Qa1
Qa2
Qa3
Qb0
Qb1
Qb2
Qb3
WE
DQM
*Note1
Row Active (A-Bank)
Read with Auto Precharge (A-Bank)
Auto Precharge Start Point (A-Bank) Row Active (B-Bank)
Read with Auto Precharge (B-Bank)
Auto Precharge Start Point (B-Bank)
: Don't care *Note 1: Any command to A-bank is not allowed in this period. tRP is determined from at auto precharge start point
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
TIMING DIAGRAM
Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMOS SDRAM
16
17
18
19
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Cb
Cc
BA0
BA1
A1 0/AP
Ra
DQ
Qa0
Qa1
Qa2
Qa3 tSHZ
Qb0
Qb1 tSHZ
Dc0
Dc2
WE
*Note 1
DQM
Row Active
Read
Clock Suspension
Read
Read DQM Write
Write DQM Clock Suspension
Write DQM
: Don't care *Note1 : DQM is needed to prevent bus contention.
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
TIMING DIAGRAM
CMOS SDRAM
Read Interrupted by Precharge Command & Read Burst Stop Cycle @ Full Page Burst
0 CLOCK CKE HIGH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CS
RAS
CAS
ADDR
RAa
CAa
CAb
BA0
BA1
A10 /AP
RAa
1
1 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
CL=2 DQ
QAa0 QAa1 QAa2
QAa3
QAa4
2
2 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
CL=3
QAa0
QAa1
QAa2 QAa3 QAa4
WE
DQM
Row Active (A-Bank)
Read (A-Bank)
Burst Stop
Read (A-Bank)
Precharge (A-Bank)
: Don't care
*Note :
1. At full page mode, burst is finished by burst stop or precharge. 2. About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated above timing diagram. See the label 1, 2 on them. But at burst write, Burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of "Full page write burst stop cycle". 3. Burst stop is valid at every burst length.
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
TIMING DIAGRAM
CMOS SDRAM
Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full Page Burst, tRDL=1CLK
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE
HIGH
CS
RAS
CAS
ADDR
RAa
CAa
CAb
BA0
BA1
A10/AP
RAa tBDL
*Note 1
tRDL
*Note 1,2
DQ
DAa0
DAa1
DAa2
DAa3 DAa4
DAb0
DAb1
DAb2
DAb3
DAb4
DAb5
WE
DQM
Row Active (A-Bank)
Write (A-Bank)
Burst Stop
Write (A-Bank)
Precharge (A-Bank) : Don't care
*Note :
1. At full page mode, burst is finished by burst stop or precharge. 2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length.
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
TIMING DIAGRAM
CMOS SDRAM
Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full Page Burst, tRDL=2CLK
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE
HIGH
CS
RAS
CAS
ADDR
RAa
CAa
CAb
BA0
BA1
A10/AP
RAa tBDL
*Note 1 *Note 1,2
tRDL
DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
DQ
DAa0
DAa1
DAa2
DAa3 DAa4
WE
DQM
Row Active (A-Bank)
Write (A-Bank)
Burst Stop
Write (A-Bank)
Precharge (A-Bank) : Don't care
*Note :
1. At full page mode, burst is finished by burst stop or precharge. 2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length.
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
TIMING DIAGRAM
Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4
0 CLOCK
tSS
CMOS SDRAM
1
2
3
~ ~ ~ ~
4
5
6
7
8
9
~ ~
10
11
12
13
14
15
16
17
18
19
tSS
*Note 2 ~ ~
CKE
*Note 1
tSS
~ ~
*Note 2
*Note 3
~ ~
CS
~ ~
RAS
~ ~
~ ~
~ ~
CAS
~ ~
~ ~
ADDR
Ra
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
Ca
~ ~
~ ~
BA
~ ~
~ ~
A10/AP
Ra
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
tSHZ
~ ~ ~ ~
DQ
Qa0
Qa1
Qa2
~ ~
WE
~ ~
~ ~
DQM
~ ~
Precharge Power-down Entry
Row Active
~ ~
~ ~
~ ~
~ ~
Read
Precharge
Precharge Power-down Exit
Active Power-down Entry
Active Power-down Exit
: Don't Care
*Note :
1. Both banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1CLK + tss prior to Row active command. 3. Can not violate minimum refresh specification. (64ms)
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
TIMING DIAGRAM
Self Refresh Entry & Exit Cycle
0 CLOCK
*Note 2 *Note 1
CMOS SDRAM
1
2
3
4
5
6 ~ ~
7
8
9
10
11
12
13 ~
14
15
16
17
18
19
*Note 4
tRCmin
*Note 6 *Note 3
CKE
tSS
~
~
CS
*Note 5
~
~
RAS ~ ~ ~
*Note 7
~
CAS ~ ~ ~
Self Refresh Exit
~
ADDR
~
~
BA0 ~BA1
~
~
A10/AP
~
~
~
WE
~
~
DQM
~
Self Refresh Entry
~ ~
~ ~
~ ~
~ ~
~
DQ
Hi-Z
Hi-Z
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~
~
Auto Refresh : Don't care
*Note :
TO ENTER SELF REFRESH MODE 1. CS, RAS & CAS with CKE should be low at the same clcok cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE. 3. The device remains in self refresh mode as long as CKE stays "Low". cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System clock restart and be stable before returning CKE high. 5. CS starts from high. 6. Minimum tRC is required after CKE going high to complete self refresh exit. 7. 4K cycle(64Mb ,128Mb) or 8K cycle(256Mb) of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh.
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
TIMING DIAGRAM
Mode Register Set Cycle
0 CLOCK CKE CS
*Note 2
CMOS SDRAM
Auto Refresh Cycle
6 7 8 9 0 10 1 11 2 12 3 13 4 14 5 15 6
~ ~
1
2
3
4
5
16 7
17 8
18 9
19 10
HIGH
RAS
*Note 1
CAS
*Note 3
ADDR
Key
Ra
BA0
BA1
WE
DQM
MRS
New Command
Auto Refresh
~ ~
~ ~
~ ~
~ ~
~ ~
DQ
Hi-Z
Hi-Z
~ ~
~ ~
~ ~
~ ~
~ ~
tRC
~ ~
~ ~
HIGH
New Command
: Don't care
* All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE *Note : 1. CS, RAS, CAS, BA0, BA1 & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table.
ELECTRONICS
Mobile DRAM (VDD 2.5V, VDDQ 1.8V & 2.5V)
TIMING DIAGRAM
Extended Mode Register Set Cycle
0 CLOCK CKE CS
*Note 2
CMOS SDRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
RAS
*Note 1
CAS
*Note 3
ADDR
Key
Ra
BA0
BA1
DQ
Hi-Z
WE
DQM
EMRS
New Command
ELECTRONICS

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